Guest columnist Paul Double, managing director of EDA Solutions, believes there is a well-entrenched and long-held view in the industry that for Asic design, in the digital, analogue or mixed-signal domain, the only tools that will to deliver a workable solution are those from the major EDA tool companies.
It can be argued that for leading-edge SoC processors in 28nm technology, a multi-million dollar tool flow might be necessary. However, it’s also a realistic proposition to use comparatively low-cost tools in the design of ‘mainstream’ Asics.
There are a host of EDA tools targeting the design of mixed-signal Asics that offer close to the same levels of functionality and performance. Backed up by access to foundry PDKs, these tools can offer productivity and cost-effectiveness.
There are thousands of mainstream analogue and mixed-signal Asics in mature process technologies, with volumes in the millions, being produced in foundries in Europe and elsewhere. These designs could include a few million gates in a 0.13- or 0.18-micron process running at a few hundred megahertz.
These are not trite designs and are well within the capabilities of cost-effective tools, which have all the functionality required by designers at mature technology nodes.
Tanner EDA, on the analogue and mixed-signal side, and Incentia Design Systems in the digital domain, have developed tools for mainstream Asic designs.
A major shift in Asic design over the past few years is increased concern about the cost of ownership of EDA tools.
Primarily, the larger tool vendors issue time-based licenses. A company may invest in one or two years of time-based licenses, when a budget review is scheduled for future licenses.
Price increases and functionality changes are always a surprise during the license renewal negotiations. Hence, there is a renewed interest in perpetual licenses.
After the initial cost of a perpetual license the only cost beyond this is the annual maintenance fee, for user support and software upgrades.
Also, companies obtain security of product. For example, if five years after initial production a re-spin of the design is required, then the same tools will be available to them. So there is the flexibility to choose the most suitable licensing model for projects and budgetary constraints.
Design Flow
Looking at a typical low-cost design flow (see Fig. 1) and starting with digital simulation, one option is the Riviera-PRO mixed-language RTL and gate-level simulator from Aldec.
It includes debugging and support of verification methodologies with SystemC and SystemVerilog, Assertions Based Verification (ABV), Transaction Level Modelling (TLM) and VHDL/Verilog Design Rule Checking (DRC).
For synthesis, a similar case can be made for cost-effective tools. In addition to providing basic synthesis functionality with the DesignCraft tool from Incentia, also on offer are a host of add-ons to make a world-class design flow.
DesignCraft supports standard gate library formats and allows designers to turn RTL code into gate-level VHDL or Verilog, and also offers the integrated capability to optimize for area, power, timing, and design-for-testability (DFT).
Also, the Incentia timing and power analysis and optimization tools are best-in-class tools, setting timing constraints and delivering power optimization at the synthesis level, which can lead to a significant reduction in consumption.
Digital place-and-route is a function that can be executed very efficiently in isolation. A gate-level netlist can be run through a place-and-route tool providing the physical layout and a timing file for re-simulation.
And because the function is very portable, there are a couple of low-cost options for design teams. If it’s a modest requirement, then Tanner EDA has an excellent low-cost tool for basic place-and-route requirements, which is in the sub-100k gate region and for circuits where timing-driven layout is not critical.
A second option, if it’s a more exacting requirement, is to use a design services company or the target foundry to provide this service. For two or three designs per year, it can be a very cost-effective approach, compared to buying an annual license for tools from the leading vendors.
The analogue design flow, essentially follows the traditional approach: schematic entry; simulation via spice; and full-custom layout, although this include some semi-automated tasks. It’s necessary to repeat the schematic entry and simulation loop a few times to ensure correct circuit operation. Following sign-off, the schematic design is passed through to analogue layout, which automatically generates all the basic components in the schematic, so all the designer has to do is the place and route.
Tanner’s HiPer DevGen layout tool also features an advanced acceleration program that will identify and automatically generate key circuit elements with a wide range of additional constraint information, ensuring that any process-related effects are taken into account.
Top-level layout brings together the analogue and digital in a single chip, with connectivity information extracted from the layout to verify correct performance. The post-layout analogue and mixed-signal (AMS) co-simulation has the analogue simulated in spice and the digital simulated in the VHDL or Verilog simulator. A Tanner interface tool provides the handshaking between the two domains.
Once circuit performance is established, full chip verification is run including LVS (Layout Versus Schematic) for both the analogue and digital, top-level verification to ensure everything is connected correctly, and DRC (Design Rule Checking) to confirm the chip is ready for manufacture at the target foundry. Once satisfied, the GDSII
