Cadence Design Systems has announced protocol and memory model verification intellectual property (IP) that supports high speed chip interface standards including LPDDR3, MIPI CSI-3 and USB 3.0 on-the-go, for use in mobiles.
This is a recognition of the level of processing power now used in smartphones and tablets for video, audio and storage.
"MIPI Alliance continues to advance mobile interface standards with processor and peripheral protocols that streamline system development and expand the sophistication of today's mobile devices," said Joel Huloux, chairman of the board, MIPI Alliance.
"By ensuring verification support for these protocols at the earliest stage possible, companies such as Cadence enable mobile designers to embrace the latest standards and deliver products that transform the consumer's mobile experience," said Huloux.
Earlier this year, Cadence added support for ARM's AMBA 4 Coherency Extensions protocol (ACE), which supported the development of multiprocessor mobile devices, and the DFI 3.0 specification, which defines an interface protocol between DDR memory controllers and PHYs.
The firm's VIP offering for mobile applications with support for the following standards:
LPDDR3: This low-power version of the pervasive DDR3 memory standard enables customers to meet the high bandwidth and power efficiency requirements of mobile systems.
MIPI CSI-3: Providing an advanced processor-to-camera sensor interface, MIPI CSI-3 enables mobile devices to deliver the bandwidth required to enable high resolution video and 3D.
MIPI Low Latency Interface (LLI): This interface cuts mobile device production cost by allowing DRAM memory sharing between multiple chips.
USB 3.0 On-The-Go (OTG): Providing 10x the performance of the previous USB specification, USB 3.0 OTG allows consumers to rapidly transfer data, such as video and audio content, as well as quickly and effortlessly charge devices.
Universal Flash Storage (UFS): A common flash storage specification for mobile devices, UFS, a JEDEC standard, is designed to bring higher data transfer speed and increased reliability to flash memory storage.
eMMC4.5: Designed for secure, yet flexible program code and data storage, eMMC4.5, a JEDEC standard, enables high bandwidth, low pin-count solutions that simplify system design.
cJTAG: With its support for reduced pin count
"In order to leverage these standards, our customers need solutions that can accurately test the functionality of their design and ensure manufacturing success," said Ziv Binyamini, corporate v-p research and development at the system realization group at Cadence.
www.cadence.com
