At the sub-micron level, engineers have traditionally been forced to deal with variation either by over-margining or under-designing. Amit Gupta CEO of Solido Design Automation. suggests a technique which offers accuracy in fewer simulations than traditional PVT corner and Monte Carlo analysis.
As process geometries continue to shrink, so the need for variation-aware custom IC design grows. It’s a fact of design life that is increasingly recognised by the electronic design community.
Variation impacts the full spectrum of custom IC designs from analog/mixed-signal, RF and I/O through to memory and standard cell libraries. It results in actual silicon performance and yield differing from that predicted in simulation and is caused by such factors as global and local random effects, environmental (voltage, temperature, load etc) issues and layout dependent effects such as proximity.
At the sub-micron level, engineers have traditionally been forced to deal with variation either by over-margining or under-designing.
Over-margining leaves significant performance, power and area on the table. Under-designing results in yield failures. Both methods are costly as they either vastly under-utilise the benefits of node migration or waste money on failed silicon.
Variation problems can be broadly categorised as process-voltage-temperature (PVT), Monte Carlo statistical, high-sigma Monte Carlo statistical or proximity issues.
PVT corner design is slow due to the increasing number of corners required to bound the effects of variation. Guessing which PVT corners are worst-case leads to inaccuracies. Additionally, the PVT corners don’t always reflect the actual worst-case corners, so a closer look at random variation becomes important.
Thorough Monte Carlo analysis has generally been so time-consuming that it is expensive to incorporate in any design flow. Furthermore, attempts to speed up Monte Carlo analysis by reducing the number of samples compromises accuracy.
Designing for proximity effects involves trading off costly schematic and layout iterations against over-designing and blowing out area. Resolving the dilemma of enabling sufficiently rapid design iterations at the same time as using an accurate model of variation requires specialist tools capable of scaling with design complexity.
These specialist tools must also be well-integrated with the custom IC solutions provided by the leading EDA tool vendors and also take full advantage of the variation models provided by foundries. They must also go beyond purely analysing the impact of variation and enable the identification of electrical hotspots as well as providing the means to fix specification failures.
One technique which includes optimal sampling and design-specific corners can be used to avoid the trade-off of accuracy versus the speed of results.
Optimal sampling employs efficient algorithms that return the same accuracy of results in far fewer simulations than traditional PVT corner and Monte Carlo analysis.
Design-specific corners comprise a reduced number of representative corners that can be simulated quickly to accurately capture boundaries of variation, including environmental and random variation.
These techniques can be used without disrupting existing, standard design flows.
For high-sigma problems, optimal sampling techniques can speed-up up the process without loss of accuracy. For proximity problems, the key is adaptive sampling combined with sensitivity analysis. By placing guard-bands only where they are needed, area can be reduced by upwards of 50% and over-design avoided. By giving visibility to proximity variation earlier in the design flow, under-design is also avoided.
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