Fujitsu Semiconductor Europe and the Fraunhofer Institute for Integrated Circuits (IIS) are collaborating to make 90nm and 65nm Asic devices more accessible to designers in multi-project wafers.
Fujitsu is making available its analogue and digital nanometre technology libraries, IP (intellectual property) pool and expertise. Fraunhofer IIS is complementing this with its own IP and design capability.
“This co-operation grants cost-effective and dependable access to the latest nanometre technology for research projects, pilot series and products,” said Josef Sauerer, head of IC design at Fraunhofer IIS.
Chip designs, right up to the GDSII data, are developed and evaluated together with customers.
Fujitsu is producing prototypes in 90nm and 65nm process technologies on multi-project wafers (MPW) at reduced mask costs.
“We are very pleased to be able to work together with such an experienced design partner as Fraunhofer IIS, and believe our co-operation will provide significant benefits to developers requiring access to advanced process technologies,” said Mark Ellins, director for Asic and Foundry Services at Fujitsu Semiconductor Europe.
There is potential for business models from prototypes (MPWs) via small series through to series production.
